The present invention relates to the control of modules connected to a bus line, and more particularly, to the setting of device addresses.
Modules arranged both inside and outside of a computer may be connected to a common line, which is used to exchange information (bus connection). In such a bus connection, an address is set for each module. Further, a control module (master) transmits a command, which includes the address of a controlled module (slave). Each slave compares the received controlled address with its own preset address. When the controlled address and preset address are the same, the slave responds to the command.
Communication systems may use an I2C (Inter-Integrated Circuit) serial transfer bus that uses two signal lines, one for a serial data (SDA) signal and the other for a serial clock (SCL) signal. These signals are in compliance with an I2C communication protocol.
The number of modules may be increased in, for example, a touch sensor, to increase the number of touch keys. This would allow a user to select a plurality of addresses and make the product more appealing.
When using sensors that function as I2C communication slaves, an address must be set for each slave. To allow the user to easily set the address, each module has an address input terminal (ADDR terminal), and an address is selected in accordance with the input level of the ADDR terminal. The easiest way to set the address would be to use the ADDR terminal as a digital input that detects a binary value. However, the number of ADDR terminals must be increased to connect more modules to the communication bus. Thus, in a sensor that has many packages that have few terminals, it would be difficult to provide many terminals just for use as address inputs.
Accordingly, techniques for setting the addresses of slave modules have been developed (e.g., refer to U.S. Patent Application Publication No. 2008/0147941, page 1 and FIG. 3). In the technique described in U.S. Patent Application Publication No. 2008/0147941, a communication system includes a slave device having address pins. The slave device is coupled to a serial data line, a clock line, a power line, and a ground line. A communication circuit communicates with a master device in accordance with a communication protocol over a data transfer bus. A decoding circuit detects a first state of the address pins. The decoding circuit than detects a second state of the address pins. If one or more logic values of the address pins differs between the first and second states then, the decoding circuit decodes a slave device address as a functional relationship between the first and second states of the address pins.
However, this technique is dependent on a certain communication protocol and thus is not very versatile. Further, the technique uses delay elements, and the operational characteristics are strongly affected by process variations that may occur during manufacturing. Thus, the technique is not well suited for integration. Further, the comparison and detection of each state must be performed at appropriate times.